Modern ICs, such as PLDs, have increased, and continue to increase, in complexity. Typical PLDs contain several tens of millions of transistors. On the one hand, the increased complexity of the circuitry has resulted in improved performance levels and increased flexibility. On the other hand, the complexity and the large number of transistors has resulted in increased power consumption in the devices. As device dimensions decrease, power consumption becomes a more critical concern. This trend will likely continue, as the complexity of ICs increases.
To help optimize usage of IC resources and to generally come up with more optimal designs, IC providers seek to provide users and designers with better power models for the various resources present. Conventional power models have focused on the cell or block levels. In other words, they do not attempt to model the power behavior of the internal circuitry of a block to a relatively significant level. This approach, however, tends to over- or under-estimate power consumption of a given block or circuit. A need therefore exists for better power models for circuitry within ICs, such as programmable logic and programmable interconnect within PLDs.